Real Time Implementation of H.264 Decoder for Heterogeneous Multicore Architectures

Principal Investigator’s Organization (PIO):

Muhammad Ali Jinnah University, Islamabad

Principal Investigator (PI):

Dr. Imtiaz Ahmed Taj, Mr. Tahir Awan


The high compression provided by H.264 comes at the expense of high computational complexity and requires a lot of processing power. To cater for this kind of processing power, the latest trends are based on multicore media processor solutions for embedded devices. Multicore media processors are based on the idea of scalability of processing cores rather than the clock speed, thus providing high processing power by avoiding the limiting factor of power consumption at high clock speed. The task being tackled here is the analysis, design and porting of the H.264 video decoder to run on heterogeneous multi-core processors. The focus is to develop software architecture to address the issues of parallel processing, synchronization and interprocess communication to meet the needs of different heterogeneous multicore architectures. The proposed architecture is ported to TI’s DM 6467 heterogeneous multicore chip for real time H.264 decoding. With digital multimedia becoming a part of our daily lives, the proposed solution is a step towards facilitating product development in this field and existing multimedia OEMs will greatly benefit from this development. Key benefits of this project are given below: • Companies all over the world developing multimedia consumer products come under the category of direct customers / beneficiaries of the project. These multimedia products range from handheld multimedia devices, IPTV and video playback devices etc. These solutions are based on different multimedia processors. The cost effectiveness of the solution can be an important factor, especially when the products are developed in large numbers.

  • Researchers and companies working on the multimedia technologies can use the outcome of the project to evaluate different heterogeneous multi-core processors as a candidate for their solution and H.264 as a targeted video decoder.
  • Researchers and companies working on multi-core multimedia processors may be able to get helpful insight into the bottlenecks that arise while porting data and computational intensive video decoders to multiple cores and may be able to counter these bottlenecks based on the outcomes of this project.

Start Date 01-Jan-2009

Duration 23 months + 8 months extension

Budget PKR 14.98 million

Status  Project Successfully Completed

Progress Report View Progress Report

Publications  N/A

Thematic Area  Other

Project Website