Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0)

Principal Investigator’s Organization (PIO):

School of Electrical Engineering & Computer Science, NUST, Islamabad

Principal Investigator (PI):

Dr. Nazar Abbas Saqib, Mr. Jahangir Hashmi

Summary

This project was to develop a suite of low power, configurable and high speed USB 3.0 IP cores including IPs for USB 3.0 host controller, USB 3.0 device controller and USB 3.0 support functions to meet the needs of this “poised-to-explode” market. This was a joint venture between NUST and their industrial partner Whizz Silicon. The project produced a patent which was filed in 2011. The IP Suite developed will support USB 3.0 which will enable data transfer of 4.8 Gb/s. It has developed architecture and the micro-architectures for the Host and Device controllers and test plan for verification of controllers.

Start Date 01-Jun-2009

Duration 30 months

Budget PKR 35.49 million

Status  Closed Project

Progress Report View Progress Report

Publications   N/A

Thematic Area  Other

Project Website 
http://asicfpga.seecs.