Design and Development of Application-Specific FPGA/Reconfigurable Hardware Generator.

Principal Investigator’s Organization (PIO):

PAF-KIET, Karachi

Principal Investigator (PI):

Dr. Muhammad Mohiuddin
Dr. Husain Parvez


This project comprised the design and development of a GUI-based platform that can be used to explore and generate different types of reconfigurable architectures. Exploration and generation of different reconfigurable architectures including FPGA, ASIF, Regular ASIF, FPGA-to-ASIC, and RNoC were supported by this platform. These alternate FPGA (reconfigurable) architectures can be optimized for target applications in terms of area, speed and/or power consumption.
The output of this tool were VHDL files of the optimized FPGA architecture and can be translated into GDSII format files for fabrication using third-party tools.